Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in todays ever shrinking and changing transistor devices. One of the principal reasons the industry is investigating replacing polysilicon gate electrodes with metal gate electrodes is to solve polysilicon depletion effects for future CMOS devices. Traditionally, polysilicon gate electrodes with overlying silicides have been used for the gate electrodes in CMOS devices. However, as device feature sizes continue to shrink, polysilicon depletion is becoming of greater concern.
To address these problems, metal gates have been proposed. One process that has been used is a full silicidation process (FUSI), which involves the use of a metal to fully silicide a conventional polysilicon gate. Examples of the metal used in the FUSI process include nickel and cobalt. However, this FUSI process is not without its own problems. For example, while the nickel silicide has worked well on larger line widths, it is believed that the industry will begin experiencing nucleation problems of the nickel as line widths continue to shrink. Also, there is the risk that a reaction of all lines across the entire wafer will not occur down to the gate/gate oxide interface. Further, excessive silicon consumption in the source/drain regions results from the thermal processes required to fully silicide the gate to the gate/gate oxide interface.
Further, to optimize the threshold voltage (Vt) in CMOS devices, metals with the appropriate work functions (e.g., from the silicon valence band to that of the conduction band) are required. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1˜4.4 eV for NMOS and 4.8˜5.2 eV for PMOS.
Unfortunately, both material and processing issues arise while attempting to manufacture metal gates having different work functions, a couple of which have been described above. In addition to those problems, another exemplary problem is that different metal gate material is used for the NMOS devices and the PMOS devices. Unfortunately, the integration of two different metals in a CMOS device flow is difficult, for example requiring significant changes to the CMOS process flow. Ideally, a single metal-containing layer would be preferred, with a portion of the single metal-containing layer being exposed to a specific process to adjust the work function of the exposed portion. This, however, is a difficult technique to perfect.
Accordingly, what is needed is a method for manufacturing metal gate structures for CMOS devices that provides better control of the silicidation process and without experiencing the drawbacks of the prior art methods.